This invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device including a plurality of logic elements and memory elements formed on the same substrate, and a method of manufacturing such a semiconductor device.
Semiconductor devices including logic elements and memory elements formed on the same substrate have been conventionally proposed.
In such conventional semiconductor devices, different problems exist depending upon whether memory elements to be formed on the same substrate as that on which logic elements are formed are of SRAM or DRAM structure, or EPROM or EEPROM structure, respectively.
Initially, where the memory element is SRAM or DRAM structure, since a memory capacity more than a predetermined value (e.g., 256 k bits) is generally required as the memory capacity, it is necessary to allow the element isolation width by the field oxide film to be finer than in the case of the logic element. To realize this, the impurity concentration of the field inversion preventive layer must be higher than that in the case of forming only logic elements in order to prevent a punch-through. Thus, a field inversion preventive layer having a high concentration will be also formed on the logic element side.
However, when such a field inversion preventive layer having a high concentration is formed on the logic element side in this way, a large electric capacitor is formed between element formation region and the field inversion preventive layer adjacent to each other resulting in the problem that the operating oposed on the logic element side is retarded.
On the other hand, also in the case where the memory element is of EPROM or EEPROM structure, a memory capacity more than a predetermined value is similarly required. For this reason, the impurity concentration of the field inversion preventive layer must be higher than that in the case of forming only logic elements on the substrate. However, since a junction withstand voltage capable of withstanding a high program voltage is required at the same time, it is necessary to lower the impurity concentration of the portion adjoining the device formation region of the field inversion preventive layer. Accordingly, the impurity concentration of the field inversion preventive layer in this case must be lower than that in the case of forming only logic elements on the substrate at the portion adjoining the device formation region, and must be higher than that in the same case as above at the central portion which does not adjoin the device formation region. However, since both field inversion preventive layers have been conventionally formed at the same time as described above, there is a problem that such layers having different concentrations are unable to be formed.